TS7001
A Micropower, 2-channel, 187.5-ksps, Serial-Output 12-bit SAR ADC
FEATURES
DESCRIPTION
Pin-for-pin, 1.5x Faster Upgrade to AD7887
Single-supply Operation: +2.7V to +3.6V
INL: ±1LSB
One or Two Single-ended Analog Inputs
Internal Wide-bandwidth Track-and-Hold
Integrated +2.5-V Reference
Flexible Power/Throughput-Rate Management
0.85mA at 187.5ksps (Internal VREF ON)
0.7mA at 187.5ksps (Internal VREF OFF)
Shutdown-mode Supply Current: 1μA (max)
SPI®/QSPI™/MICROWIRE™/DSP-Compatible
Serial Interfaces
1
Operating Temperature Range: -40ºC to +85ºC
8-pin MSOP Packaging
The TS7001 – a pin-for-pin, 1.5x faster alternate to
the AD7887 - is a self-contained, 2-channel, high-
speed, micropower, 12-bit analog-to-digital converter
(ADC) that operates from a single +2.7V to +3.6V
power supply. The TS7001 is capable of a 187.5-ksps
throughput rate with an external 3 MHz serial clock
and draws 0.85mA supply current.
The wideband input track-and-hold acquires signals
in 500ns and features a single-ended sampling
topology. Output data coding is straight binary and
the ADC is capable of converting full power signals
up to 10 MHz. The ADC also contains an integrated
2.5V reference or the VREF pin can be overdriven by
an external reference.
The TS7001’s provides one or two analog inputs
each with an analog input range from 0 to V
REF
. In
two-channel operation, the analog input range is 0V
to VDD. Efficient circuit design ensures low power
consumption of 2mW (typical) for normal operation
and 3μW in power-down operation.
The TS7001 is fully specified from -40ºC to +85ºC
and is available in 8-pin MSOP package.
APPLICATIONS
Instrumentation and Control Systems
High-Speed Modems
Battery-powered systems:
Personal Digital Assistants, Medical
Instruments, Mobile Communications
FUNCTIONAL BLOCK DIAGRAM
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National
Semiconductor Corporation
Page 1
© 2014 Silicon Laboratories, Inc. All rights reserved.
1
TS7001
ABSOLUTE MAXIMUM RATINGS
V
DD
to AGND ................................................................
−0.3V
to +7V
Analog Input Voltage (AIN0, AIN1) to AGND ....
−0.3V
to V
DD
+ 0.3V
Digital Input Voltage to AGND...........................
−0.3V
to V
DD
+ 0.3V
Digital Output Voltage to AGND ........................
−0.3V
to V
DD
+ 0.3V
REFIN/REFOUT to AGND ................................
−0.3V
to V
DD
+ 0.3V
Input Current to Any Pin Except Supplies
1
............................. ±10mA
Operating Temperature Range ..............................
−40°C
to +125°C
Storage Temperature Range .................................
−65°C
to +150°C
Junction Temperature ........................................................... +150°C
MSOP Package Power Dissipation ....................................... 450mW
θ
JA
Thermal Impedance .............................................. 205.9°C/W
θ
JC
Thermal Impedance .............................................. 43.74°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) ........................................................ 215°C
Infrared (15 sec) ................................................................ 220°C
Pb-Free Temperature, Soldering Reflow ............................. 260(0)°C
ESD ............................................................................................. 4kV
Electrical and thermal stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections
of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and
lifetime.
PACKAGE/ORDERING INFORMATION
ORDER NUMBER
TS7001IM8
PART MARKING
TADF
CARRIER
Tube
Tape & Reel
QUANTITY
50
2500
TS7001IM8T
Lead-free Program:
Silicon Labs supplies only lead-free packaging.
Consult Silicon Labs for products specified with wider operating temperature ranges.
Page 2
TS7001 Rev. 1.0
TS7001
ELECTRICAL CHARACTERISTICS
V
DD
= +2.7V to +3.6V; V
REF
= 2.5V External/internal reference unless otherwise noted; f
SCLK
= 3 MHz;
T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Parameter
DYNAMIC PERFORMANCE
Signal to Noise + Distortion Ratio (SNR)
2
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second-Order Terms
Third-Order Terms
Channel-to-Channel Isolation
Full-Power Bandwidth
DC ACCURACY(Any channel)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Offset Error Match
Gain Error
Gain Error Match
ANALOG INPUT
Input Voltage Range
Leakage Current
Input Capacitance
REFERENCE INPUT/OUTPUT
REFIN Input Voltage Range
Input Impedance
REFOUT Output Voltage
REFOUT Temperature Coefficient
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN3
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
4
Output Coding
CONVERSION RATE
Throughput Time
Track-and-Hold Acquisition Time
Conversion Time
16
1.5
14.5
SCLK cycles
SCLK cycles
SCLK cycles
Conversion time plus acquisition time is 187.5ksps,
with 3 MHz Clock
4.833
μs
(3 MHz Clock)
Limit
1
71
−80
−80
−80
−80
−80
10
12
±1
±1
±4
±6
0.5
±2
±1
±6
2
0 to VREF
0 to VDD
±5
10
2.5/VDD
10
2.488/2.513
30
2.1
0.8
±1
10
V
DD
−
0.5
0.4
±1
10
Straight
(Natural)
Binary
Unit
dB (typ)
dB (typ)
db (typ)
dB (typ)
dB (typ)
dB (typ)
MHz (typ)
Bits
LSB (max)
LSB (max)
LSB (max)
LSB (typ)
LSB (max)
LSB (typ)
LSB (max)
LSB (typ)
LSB (max)
V
V
μA
(max)
pF (typ)
V (min/max)
kΩ (typ)
V (min/max)
ppm/°C (typ)
V (min)
V (max)
μA
(max)
pF (max)
V (min)
V (max)
μA
(max)
pF (max)
V
DD
= 2.7V to 3.6V, I
SOURCE
= 200
μA
I
SINK
= 200
μA
Single-channel/Dual-channel; Functional from 1.2V
Very high impedance if internal reference is disabled
Initial accuracy = 0.5%
Test Conditions/Comments
f
IN
= 10 kHz sine wave, f
SAMPLE
= 187.5ksps
f
IN
= 10 kHz sine wave, f
SAMPLE
= 187.5ksps
f
IN
= 10 kHz sine wave, f
SAMPLE
= 187.5ksps
f1 = 9.983 kHz, f2 = 10.05 kHz, f
SAMPLE
= 187.5ksps
f1 = 9.983 kHz, f2 = 10.05 kHz, f
SAMPLE
= 187.5ksps
f
IN
= 25 kHz
Measured at 3 dB down
VDD = 3V
VDD = 3V; Guaranteed no missing codes to 11 bits
VDD = 3V, dual-channel mode
Single-channel mode
Dual-channel mode
Single-channel mode, external reference
Single-channel mode, internal reference
Single-channel operation
Dual-channel operation
VDD = 2.7V to 3.6V
VDD = 2.7V to 3.6V
Typically 10nA, V
IN
= 0V or VDD
TS7001 Rev. 1.0
Page 3
TS7001
ELECTRICAL SPECIFICATIONS (continued)
V
DD
= +2.7V to +3.6V; V
REF
= 2.5V External/internal reference unless otherwise noted; f
SCLK
= 3 MHz;
T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Parameter
POWER REQUIREMENTS
VDD
IDD
Normal Mode
4
(PM Mode 2)
Static
Operational (f
SAMPLE
= 187.5 ksps)
Using Standby Mode (PM Mode 4)
Using Shutdown Mode
(PM Modes 1 and 3)
Standby Mode
5
Shutdown Mode
5
Normal Mode Power Dissipation
Shutdown Power Dissipation
Standby Power Dissipation
Limit
1
+2.7/+3.6
Unit
V (min/max)
Test Conditions/Comments
0.6
0.85
0.7
0.45
0.12
0.012
0.21
1
2.1
3
0.63
mA (max)
mA (typ)
mA (typ)
mA (typ)
mA (typ)
mA (typ)
mA (max)
μA
(max)
mW (max)
μW
(max)
mW (max)
Internal reference enabled
Internal reference disabled
f
SAMPLE
= 50 ksps
f
SAMPLE
= 10 ksps
f
SAMPLE
= 1 ksps
VDD = 2.7V to 3.6V
VDD = 2.7V to 3.6V
VDD = 3 V
VDD = 3 V
VDD = 3 V
Note 1:
The TS7001’s temperature range is –40°C to +85°C.
Note 2:
SNR calculation includes distortion and noise components.
Note 3:
Sample tested at T
A
= 25°C to ensure compliance.
Note 4:
All digital inputs at GND except for CS at V
DD
. All digital outputs are unloaded. Analog inputs are connected to GND.
Note 5:
SCLK is at GND when SCLK is off. All digital inputs are at GND except for CS at VDD. All digital outputs are unloaded. Analog inputs
are connected to GND.
Page 4
TS7001 Rev. 1.0
TS7001
TIMING SPECIFICATIONS
1
V
DD
= +2.7V to +3.6V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Parameter
f
SCLK2
t
CONVERT
t
ACQ
t
1
t
23
t
33
t
4
t
5
t
6
t
7
t
84
t
9
Limit
3
14.5 × t
SCLK
1.5 × t
SCLK
10
60
100
20
20
0.4 × t
SCLK
0.4 × t
SCLK
80
5
Unit
MHz (max)
Description
External serial clock
Conversion Time
Throughput Time = t
CONVERT
+ t
ACQ
= 16 t
SCLK
ns (min)
ns (max)
ns (max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
μs
(typ)
CS to SCLK Setup Time
Delay from CS until DOUT three-state disabled
Data Access Time after SCLK High-to-Low Edge
Data Setup Time prior to SCLK Low-to-High Edge
Data Valid to SCLK Hold Time
SCLK high Pulse Width
SCLK low Pulse Width
CS rising edge to DOUT High-Z
Power-up Time from Shutdown
Note 1:
Timing specifications are sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of
VDD) and timed relative to a voltage level of 1.6V.
Note 2:
The mark/space ratio for the SCLK input is 40/60 to 60/40. See Serial Interface section for additional details.
Note 3:
Measured with the load circuit as shown below and defined as the time required for the output to cross 0.8V or 2.0V.
Note 4:
Timing specification t
8
is derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit shown
below. The measured result is then extrapolated back to remove the effects of charging or discharging the 50pF capacitor. This
means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish time of the TS7001 and is independent of bus
loading.
Load Circuit Used for TS7001’s Digital Output Timing
Specifications.
TS7001 Rev. 1.0
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